CROSSTALK NOISE REDUCTION USING WIRE SPACING IN VLSI RC GLOBAL INTERCONNECTS Anushree

ABSTRCAT This paper presents a closed form 2π crosstalk noise model for on-chip VLSI RC interconnects. It considers a case when unit step input is applied to the aggressor which is adjacent to the victim net and producing crosstalk noise effect over it. In the next section closed form formulae for crosstalk noise pulse width and noise amplitude for RC interconnect have been derived for mathematical implementation of this crosstalk noise. Further, we consider the effect of separation between aggressor and victim lines over crosstalk noise voltage expressions (peak value and width).